A 14bit 500MS/s 85.62dBc SFDR 66.29dB SNDR SHA-less pipelined ADC with a stable and high-linearity input buffer and aperture-error calibration in 40nm CMOS
نویسندگان
چکیده
This paper presents a 14bit 500MS/s SHA-less pipelined analog-to-digital converter (ADC) implemented in 40nm CMOS. A high-linearity pseudo-differential push-pull input buffer with an anti-oscillation technique and nonlinear parasitism eliminate is proposed to stably drive the stages while keeping low distortion. Moreover, digital controlled aperture-error calibration also employed offset of comparators compensated advance. Measurement results show that ADC achieves signal-to-noise-and-distortion-ratio (SNDR) 66.29dB spurious-free-dynamic-range (SFDR) 85.62dBc at 80.1MHz input.
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ژورنال
عنوان ژورنال: IEICE Electronics Express
سال: 2021
ISSN: ['1349-2543', '1349-9467']
DOI: https://doi.org/10.1587/elex.18.20210171